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Features
* Comprehensive Library of Standard Logic Cells * ATC25 I/O Cells Designed to Operate with VDD = 2.5V 0.25V as Main Target Operating
Conditions
* IO33 Pad Library Provides Interface to 3V Environment * Oscillators Provide Stable Clock Sources * Basic Analog Input/Output, Power, Ground and Multiplexer Cells Available,
High-performance Analog Cells Can Be Developed on Request
* Memory Cells Compiled to the Precise Requirements of the Design * Compatible with Atmel's Extensive Range of Microcontroller, DSP, Standard Interface
and Application Specific Cells
Cell-based ASIC ATC25 Summary
Description
The Atmel ATC25 CBIC family is fabricated on a proprietary 0.25 micron five-layermetal CMOS process intended for use with a supply voltage of 2.5V 0.25V. The following table shows the range for which Atmel library cells have been characterized. Table 1. Recommended Operating Conditions
Symbol VDD VDD3 VI VO TEMP Parameter DC Supply Voltage DC Supply Voltage DC Input Voltage DC Output Voltage Operating Free Air Temperature Range Industrial Conditions Core and Standard I/Os 3V Interface I/Os Min 2.25 3 0 0 -40 Typ 2.5 3.3 Max 2.75 3.6 VDD VDD +85 Unit V V V V
C
The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operating conditions; they correspond to three characterization conditions defined as follows: * MIN conditions: TJ = -40C VDD (cell) = 2.75V Process = fast (industrial best case) * TYP conditions: TJ = +25C VDD (cell) = 2.5V Process = typ (industrial typical case) * MAX conditions: TJ = +100C VDD (cell) = 2.25V Process = slow (industrial worst case) Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accurate timing estimates, all characterization has been run on electrical netlists extracted from the layout database.
Rev. 1306DS-CBIC-09/02
1
Standard Cell Library SClib
The Atmel Standard Cell Library, SClib, contains a comprehensive set of combinational logic and storage cells. The SClib library includes cells which belong to the following categories: * * * * * * Buffers and Gates Multiplexers Flip-flops Scan Flip-flops Latches Adders and Subtractors
Decoding the Cell Name
The table below shows the naming conventions for the cells in the SClib library. Each cell name begins with either a two-, three-, or four-letter code that defines the type of cell. This indicates the range of standard cells available.
Table 2. Cell Codes
Code AD AH AS AN AOI AON AOR BH BUFB BUFF BUFT CG CLK2 DE DF INV0 INVB Description Adder Half Adder Adder/Subtractor AND Gate AND-OR-Invert Gate AND-OR-AND-Invert Gates AND-OR Gate Bus Holder Balanced Buffer Non-Inverting Buffer Non-Inverting 3-State Buffer Carry Generator Clock Buffer D-Enabled Flip-Flop D Flip-Flop Inverter Balanced Inverter Code INVT JK LA MI MX ND NR OAI OAN OR ORA SD SE SRLA SU XN XR Description Inverting 3-State Buffer JK Flip-Flop D Latch Inverting Multiplexer Multiplexer NAND Gate NOR Gate OR-AND-Invert Gate OR-AND-OR-Invert Gates OR Gate OR-AND Gate Multiplexed Scan D Flip-Flop Multiplexed Scan Enable D Flip-Flop Set/Reset Latches with NAND input Subtractor Exclusive NOR Gate Exclusive OR Gate
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ATC25 Summary
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ATC25 Summary
Cell Matrices
The following three tables provide a quick reference to the storage elements in the SClib library. Note that all storage elements feature buffered clock inputs and buffered output. Table 3. JK Flip-flops
Macro Name JKBRBx Set Clear 1x Drive 2x Drive
*
*
*
*
Table 4. D Flip-flops
Macro Name DFBRBx DFCRBx DFCRQx DFCRNx DFNRBx DFNRQx DFPRBx DEPRQx DENRQx DENRBx DECRQx Set Clear Enabled D Input 1x Drive 2x Drive Single Output
*
* * * *
* * * * * *
* * * * * * * * * * * * * * * *
* * * * * * *
* * * * *
Table 5. Scan Flip-flops
Macro Name SDBRBx SDCRBx SDCRNx SDCRQx SDNRBx SDNRNx SDNRQx SDPRBx SECRQx SENRQx SEPRQx Set Clear 1x Drive 2x Drive Single Output
*
* * * *
* * * * * * *
* * * * * * * * * * * * * * * * * *
* *
* * *
*
*
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Input/Output Pad Cell Libraries IO25lib and IO33lib
Voltage Levels
The Atmel Input/Output Cell Library, IO25lib, contains a comprehensive list of input, output, bidirectional and tristate cells. The ATC25 (2.5V) cell library includes a special set of I/O cells, IO33lib, for interfacing with external 3V devices.
The IO25lib library is made up exclusively of low-voltage chip interface circuits powered by a voltage in the range of 2.25V to 2.75V. The library is compatible with the SClib 2.5volt standard cells library. Designers are strongly encouraged to provide three kinds of power pairs for the IO25lib library. These are "AC", "DC" and core power pairs. AC power is used by the I/O to switch its output from one state to the other. This switching generates noise in the AC power buses on the chip. DC power is used by the I/O to maintain its output in a steady state. The best noise performance is achieved when the DC power buses on the chip are free of noise; designers are encouraged to use separate power pairs for AC and DC power to prevent most of the noise in the AC power buses from reaching the DC power buses. The same power pairs can be used to supply both DC power to the I/Os and power to the core without affecting noise performance.
Power and Ground Pads
Table 6. VSS Power Pad Combinations
Core Vssi Switching I/O VssAC Quiet I/O VssDC Library Cell Name pv25i00
Signal Name VSS VSS VSS VSS VSS VSS
* * * * * * * * * *
pv25a00 pv25d00 pv25e00 pv25b00 pv25f00
Table 7. VDD Power Pad Combinations
Core Vddi Switching I/O VddAC Quiet I/O VddDC Library Cell Name pv25i25
Signal Name VDD VDD VDD VDD VDD VDD
* * * * * * * * * *
pv25a25 pv25d25 pv25e25 pv25b25 pv25f25
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ATC25 Summary
1306DS-CBIC-09/02
ATC25 Summary
Cell Matrices
Table 8. CMOS Pads
CMOS Cell Name PC25B01 PC25B02 PC25B03 PC25B04 PC25B05 PC25O01 PC25O02 PC25O03 PC25O04 PC25O05 PC25T01 PC25T02 PC25T03 PC25T04 PC25T05 3-State I/O Output Only 3-State Output Only Drive Strength 1x 2x 3x 4x 5x Pad Sites Used 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
* * * * * * * * * * * * * * *
1x 2x 3x 4x 5x 1x 2x 3x 4x 5x
Table 9. TTL Pads
TTL Cell Name PT25B01 PT25B02 PT25B03 PT25O01 PT25O02 PT25O03 PT25T01 PT25T02 PT25T03 3-State I/O Output Only 3-State Output Only Drive Strength 2 mA 4 mA 8 mA Pad Sites Used 1 1 1 1 1 1 1 1 1
* * * * * * * * *
2 mA 4 mA 8 mA 2 mA 4 mA 8 mA
Table 10. CMOS/TTL Input Only Pad
CMOS Cell Name PC25D01 PC25D11 PC25D21 PC25D31 Input Levels CMOS CMOS CMOS CMOS Schmitt Input Level Shifter Non-Inverting Inverting Pad Sites Used 1
* * * * * *
1 1 1
Note:
All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device.
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IO33lib Low Slew Rate Cells
The IO33lib cells comprise a series of 2.5V/3.3V input/output pads developed for low supply voltage processes in order to interface 2.5V ASICs to 3.3V environments. All IO33lib cells are slew rate controlled. Advantage has been taken of the 2.5V to 3.3V level shifter (slow by construction) to reduce the slew rate without reducing speed. Table 11. IO33lib Pads
3V Interface Pad Name pc33b0x pc33d00 pc33o0x pc33t0x 3-State I/O Output Only 3-State Output Only Input Only Drive Strength 2 mA, 4 mA, 8 mA, 16 mA Pad Sites Used 1 1 2 mA, 4 mA, 8 mA, 16 mA 1 1
* * * *
2 mA, 4 mA, 8 mA, 16 mA
Note:
All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device.
Table 12. IO33lib Power Pads
Power Bus Connections Cell Name pv33e00 pv33i00 pv33i25 pv33e33 pv33ecrn vssi mixvss vddi mixvdd Pad Sites Used 1 1
* * * * * *
1 1 2
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ATC25 Summary
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ATC25 Summary
Oscillator Cell Library Osc25lib
Crystal Oscillators
The Atmel Oscillator Library provides stable clock sources. It comprises four oscillators and one power-on-reset. The Atmel two-pad oscillators are designed with the Pierce three-point oscillator structure. For the 32.768 Hz oscillator, the load capacitance must be between 6 pF and 12.5 pF For high-frequency oscillators, the load capactance must be between 15 pF and 20 pF. External capacitors must be added in order to obtain the correct load capacitance. Clock output is high at off state (onosc = 0). The oscillators provide a bypass mode (onosc = 1), clock = not (xin). Table 13 gives the available oscillator cells. Table 13. Oscillator and POR Cells
Cell Name OSC25f33K OSC25f9M OSC25f16M OSC25f27M POR25 Description Low-power, optimized for 32.786 kHz crystal 9 MHz crystal oscillator 16 MHz crystal oscillator 27 MHz crystal oscillator Static and dynamic reset with internal hysterisis
Basic Analog Cell Library ANA25lib, ANA33lib
The Atmel CBIC analog library makes the following parts available: * Multiplexer modules - - * * Multiplexers to minimize cross-talk (for use with high-impedance nodes). Multiplexers to minimize ON resistance.
Analog input and output cells Analog power and ground cells
A special set of basic analog I/O cells, ANA33lib, is available for interfacing with external 3.3V devices.
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Atmel Compiled Megacell Library
The Atmel Compiled Megacell Library enables compilation of megacells for the functions Synchronous RAM, High-range Synchronous RAM, Asynchronous RAM, Asynchronous Dual-port RAM, Asynchronous Two-port RAM and Synchronous ROM, according to the user's precise requirements. The Atmel megacells can be instanced as often as required in designs and can be used in parallel with cells from all other Atmel CBIC libraries. All the megacell representations required for schematic entry, simulation, place and route, layout generation, and verification are created automatically.
Compiled Synchronous RAM Megacells
The Atmel Synchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous RAM megacell configurations is as follows:
Number of bits Number of words Word Size 128, .. 144K bits 32, .. 8K 4, .. 36 bits
The following table shows the range of performances for particular Synchronous RAM configurations under typical conditions.
Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz)
2
1K x 8 (8K bits) 51 305 0.17
2K x 16 (32K bits) 58 242 0.36
4K x 32 (128K bits) 62 169 0.73
Compiled High-range Synchronous RAM Megacells
The Atmel High-range Synchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted High-range Synchronous RAM megacell configurations is as follows:
Number of bits Number of words Word Size 16K, .. 2.25M bits 2K, .. 32K 8, .. 72 bits
The following table shows the range of performances for particular High-range Synchronous RAM configurations under typical conditions.
Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz)
2
8K x 8 (64K bits) 80 186 0.29
16K x 16 (256K bits) 84 120 0.55
32K x 32 (1M bits) 87 71 1.22
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ATC25 Summary
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ATC25 Summary
Compiled Asynchronous RAM Megacells
The Atmel Asynchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous RAM megacell configurations is as follows:
Number of bits Number of words Word Size 128, .. 128K bits 16, .. 4K 8, .. 36 bits
The following table shows the range of performances for particular Asynchronous RAM configurations under typical conditions.
Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz)
2
1K x 8 (8K bits) 40 380 0.24
2K x 16 (32K bits) 40 378 0.38
4K x 32 (128K bits) 50 293 0.63
Compiled Asynchronous Dual-port RAM Megacells
The Atmel Asynchronous Dual-port RAM has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous Dual-port RAM Megacell configurations is as follows:
Number of bits Number of words(1) Word Size(1) 128, .. 16K 64, .. 2K 2, .. 36 bits
Note:
1. Must be the same for both ports.
The following table shows the range of performances for particular Asynchronous Dualport RAM configurations under typical conditions.
Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz)
2
128 x 8 (1K bits) 22 305 0.09
256 x 16 (4K bits) 32 274 0.31
512 x 32 (16K bits) 36 248 0.41
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Compiled Two-port RAM Megacells
The Atmel Asynchronous Two-port RAM can be configured in multi-bank form, with a maximum of four banks, and can be used to achieve FIFO functions. The range of permitted Asynchronous Two-port RAM Megacell configurations is as follows:
Number of bits Number of words Word Size(1)
(1)
128, .. 36K 64, .. 2K 2, .. 36 bits
Note:
1. Must be the same for both ports.
The following table shows the range of performances for particular Asynchronous Twoport RAM configurations under typical conditions.
Configuration Density (Kbits/mm2) Frequency (MHz) Dynamic Power (mW/MHz) 256 x 8 (2K bits) 20 385 0.06 512 x 16 (8K bits) 24 357 0.10 1K x 32 (32K bits) 27 294 0.18
Compiled Synchronous ROM Megacells
The Atmel Synchronous ROM is diffusion programmable and is applicable in low power solutions. It can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous ROM Megacell configurations is as follows:
Number of bits Number of words Word Size 256, .. 512K 64, .. 8K 4, .. 72 bits
The following table shows the range of performances for particular Synchronous ROM configurations under typical conditions.
Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz)
2
2K x 8 (16K bits) 400 198 0.13
4K x 16 (64K bits) 568 187 0.26
8K x 32 (256K bits) 669 140 0.54
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ATC25 Summary
1306DS-CBIC-09/02
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1306DS-CBIC-09/02 0M

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